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1

Understanding branches and designing branch predictors for high-performance microprocessors

Evers, M., Tse-Yu Yeh

Journal:

Proceedings of the IEEE

Year:

2001

Language:

english

File:

PDF, 175 KB

english, 2001

2

[ACM Press 25th Anniversary International Conference - Munich, Germany (2014.06.10-2014.06.13)] 25th Anniversary International Conference on Supercomputing Anniversary Volume - - Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yeh, Tse-Yu, Marr, Deborah T., Patt, Yale N.

Year:

2014

Language:

english

File:

PDF, 1.52 MB

english, 2014

3

[ACM Press the 20th annual international symposium - San Diego, California, United States (1993.05.16-1993.05.19)] Proceedings of the 20th annual international symposium on Computer architecture - ISCA '93 - A comparison of dynamic branch predictors that use two levels of branch history

Yeh, Tse-Yu, Patt, Yale N.

Year:

1993

Language:

english

File:

PDF, 964 KB

english, 1993

4

Low-Power, High-Performance Architecture of the PWRficient Processor Family

Journal:

Year:

2007

Language:

english

File:

PDF, 765 KB

english, 2007

5

[IEEE Comput. Soc. Press 20th Annual International Symposium on Computer Architecture - San Diego, CA, USA (16-19 May 1993)] Proceedings of the 20th Annual International Symposium on Computer Architecture - A Comparison Of Dynamic Branch Predictors That Use Two Levels Of Branch History

Tse-Yu Yeh,, Patt, Y.N.

Year:

1993

Language:

english

File:

PDF, 909 KB

english, 1993

6

[IEEE Comput. Soc. Press [1992] 25th Annual International Symposium on Microarchitecture MICRO 25 - Portland, OR, USA (1-4 Dec. 1992)] [1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25 - A Comprehensive Instruction Fetch Mechanism For A Processor Supporting Speculative Execution

Tse-Yu Yeh,, Patt, Y.N.

Year:

1992

Language:

english

File:

PDF, 1.01 MB

english, 1992

7

[ACM MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture - San Jose, CA, USA (30 Nov.-2 Dec. 1994)] Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture - Branch classification: a new mechanism for improving branch predictor performance

Po-Yung Chang,, Hao, E., Tse-Yu Yeh,, Patt, Y.

Year:

1994

Language:

english

File:

PDF, 853 KB

english, 1994

8

[ACM Press 25th Anniversary International Conference - Munich, Germany (2014.06.10-2014.06.13)] 25th Anniversary International Conference on Supercomputing Anniversary Volume - - Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yeh, Tse-Yu, Marr, Deborah T., Patt, Yale N.

Year:

2014

Language:

english

File:

PDF, 593 KB

english, 2014

9

[IEEE Comput. Soc. Press 26th Annual International Symposium on Microarchitecture - Austin, TX, USA (1-3 Dec. 1993)] Proceedings of the 26th Annual International Symposium on Microarchitecture - Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors

Tse-Yu Yeh,, Patt, Y.N.

Year:

1993

Language:

english

File:

PDF, 1.08 MB

english, 1993

10

[ACM Press the 24th annual international symposium - Albuquerque, New Mexico, Puerto Rico (1991..-..)] Proceedings of the 24th annual international symposium on Microarchitecture - MICRO 24 - Two-level adaptive training branch prediction

Yeh, Tse-Yu, Patt, Yale N.

Year:

1991

Language:

english

File:

PDF, 1.08 MB

english, 1991

11

[IEEE [1992] 19th Annual International Symposium on Computer Architecture - Gold Coast, Australia (May 19-21, 1992)] [1992] Proceedings the 19th Annual International Symposium on Computer Architecture - Alternative Implementations of Two-Level Adaptive Branch Prediction

Tse-Yu Yeh,, Patt, Y.N.

Year:

1992

Language:

english

File:

PDF, 1.15 MB

english, 1992

12

[ACM Press the 18th annual international symposium - Toronto, Ontario, Canada (1991.05.27-1991.05.30)] Proceedings of the 18th annual international symposium on Computer architecture - ISCA '91 - Single instruction stream parallelism is greater than two

Butler, Michael, Yeh, Tse-Yu, Patt, Yale, Alsup, Mitch, Scales, Hunter, Shebanow, Michael

Year:

1991

Language:

english

File:

PDF, 1.16 MB

english, 1991

13

[ACM Press the 7th international conference - Tokyo, Japan (1993.07.19-1993.07.23)] Proceedings of the 7th international conference on Supercomputing - ICS '93 - Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yeh, Tse-Yu, Marr, Deborah T., Patt, Yale N.

Year:

1993

Language:

english

File:

PDF, 1.08 MB

english, 1993

14

A comprehensive instruction fetch mechanism for a processor supporting speculative execution

Yeh, Tse-Yu, Patt, Yale N.

Journal:

ACM SIGMICRO Newsletter

Year:

1992

Language:

english

File:

PDF, 1.27 MB

english, 1992

15

[ACM Press the 19th annual international symposium - Queensland, Australia (1992.05.19-1992.05.21)] Proceedings of the 19th annual international symposium on Computer architecture - ISCA '92 - Alternative implementations of two-level adaptive branch prediction

Yeh, Tse-Yu, Patt, Yale N.

Year:

1992

Language:

english

File:

PDF, 1.23 MB

english, 1992

16

A comparison of dynamic branch predictors that use two levels of branch history

Yeh, Tse-Yu, Patt, Yale N.

Journal:

ACM SIGARCH Computer Architecture News

Year:

1993

Language:

english

File:

PDF, 964 KB

english, 1993

17

[ACM Press the 27th annual international symposium - San Jose, California, United States (1994.11.30-1994.12.02)] Proceedings of the 27th annual international symposium on Microarchitecture - MICRO 27 - Branch classification

Chang, Po-Yung, Hao, Eric, Yeh, Tse-Yu, Patt, Yale

Year:

1994

Language:

english

File:

PDF, 849 KB

english, 1994

18

[ACM Press 25 years of the international symposia - Barcelona, Spain (1998.06.27-1998.07.02)] 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98 - Alternative implementations of two-level adaptive branch prediction

Yeh, Tse-Yu, Patt, Yale N.

Year:

1998

Language:

english

File:

PDF, 1.33 MB

english, 1998

19

[ACM Press 25 years of the international symposia - Barcelona, Spain (1998.06.27-1998.07.02)] 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98 - Retrospective: alternative implementations of two-level adaptive training branch prediction

Yeh, Tse-Yu, Patt, Yale N.

Year:

1998

Language:

english

File:

PDF, 215 KB

english, 1998

20

Single instruction stream parallelism is greater than two

Butler, Michael, Yeh, Tse-Yu, Patt, Yale, Alsup, Mitch, Scales, Hunter, Shebanow, Michael

Journal:

ACM SIGARCH Computer Architecture News

Year:

1991

Language:

english

File:

PDF, 1.16 MB

english, 1991

21

Alternative implementations of two-level adaptive branch prediction

Yeh, Tse-Yu, Patt, Yale N.

Journal:

ACM SIGARCH Computer Architecture News

Year:

1992

Language:

english

File:

PDF, 1.23 MB

english, 1992

22

SPIE Proceedings [SPIE Asia Pacific Symposium on Microelectronics and MEMS - Gold Coast, Australia (Wednesday 27 October 1999)] Device and Process Technologies for MEMS and Microelectronics - Stress effect on the via crack of IMD structure in scrubber processing

Huang, D. F., Yeh, R. S., Lin, Tse-Yu, Hung, Chih-Chien, Lin, T. C., Chang, Chao-Hsin, Chen, Chia-Hsiang, Chau, Kevin H., Dimitrijev, Sima

Year:

1999

Language:

english

File:

PDF, 872 KB

english, 1999

23

[IEEE 2016 IEEE Second International Conference on Multimedia Big Data (BigMM) - Taipei, Taiwan (2016.4.20-2016.4.22)] 2016 IEEE Second International Conference on Multimedia Big Data (BigMM) - Real-Time Sign Language Recognition in Complex Background Scene Based on a Hierarchical Clustering Classification Method

Pan, Tse-Yu, Lo, Li-Yun, Yeh, Chung-Wei, Li, Jhe-Wei, Liu, Hou-Tim, Hu, Min-Chun

Year:

2016

Language:

english

File:

PDF, 616 KB

english, 2016

24

Branch Classification: A New Mechanism for Improving Branch Predictor Performance

Po-Yung Chang,Eric Hao,Tse-Yu Yeh…

Journal:

International Journal of Parallel Programming

Year:

1996

Language:

english

File:

PDF, 2.43 MB

english, 1996

25

[IEEE 2006 IEEE Hot Chips 18 Symposium (HCS) - Stanford, CA, USA (2006.8.20-2006.8.22)] 2006 IEEE Hot Chips 18 Symposium (HCS) - Low-power, high-performance architecture of the PWRficient processor family

Year:

2006

Language:

english

File:

PDF, 365 KB

english, 2006

26

A Hierarchical Hand Gesture Recognition Framework for Sports Referee Training-Based EMG and Accelerometer Sensors

Pan, Tse-Yu, Tsai, Wan-Lun, Chang, Chen-Yuan, Yeh, Chung-Wei, Hu, Min-Chun

Journal:

IEEE Transactions on Cybernetics

Year:

2020

File:

PDF, 1.87 MB

2020

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